1. Field of the Invention
The invention relates generally to semiconductor devices including a double structured well and manufacturing method thereof and, more particularly, relates to techniques for improving tolerance to injection of minority carriers caused by a noise from the outside of devices.
2. Description of the Background Art
With the advancement of miniaturization and increased integration density of semiconductor devices, one semiconductor device is being developed in which wells having both p and n conductivity types are formed close to each other in the neighborhood of the surface of a semiconductor substrate such as a single crystalline silicon substrate. In many cases, wells having a double structure for example, in which a p-type well is further formed inside an n-type well, are foiled for such a semiconductor device and there has been a problem of disadvantageous phenomena, such as a latch-up due to injection of minority carriers caused particularly in semiconductor devices including wells of such a double structure. One example of a conventional semiconductor device including double structured wells is a CMOS (Complementary Metal Oxide Semiconductor) described in "Extended Abstract of the 21st Conference of Solid State Devices and Materials, Tokyo, 1989, p 105-108". A conventional semiconductor device including double structured wells will now be described with reference to FIGS. 1 to 4.
Referring to FIG. 1, in the conventional semiconductor device including double structured wells, a p well 2, an n well 3 and an n well 4 are formed on the surface of a p-type silicon substrate 1 A p well 5 is further formed inside n well 3, and p well 2 and n well 4 are formed adjacent to the side portions of n well 3.
The operation in the structure of the conventional double structured wells above will now be described with reference to FIG. 1. When a voltage lower than that of a terminal 14 connected to a p.sup.+ layer is instantaneously applied to a terminal 13 connected to an n.sup.+ layer within p well 5, a current flows from terminal 14 to terminal 13. At this time, minority carriers of electrons are injected into p well 5 from terminal 13. The arrow A shown in FIG. 1 indicates the direction of the flow of the current in a solid line and the direction of the flow of the electrons in a broken line in this case. Though the minority carriers of electrons diffuse in the direction toward p well 2 as well, they are captured by the positive bias applied to a terminal 12 connected to an n.sup.+ layer on the surface of n well 3, so that they do not reach p well 2.
The operation above can be also described in the same way, replacing terminal 13 and terminal 14 with terminal 15 and terminal 16, respectively, and further replacing p well 2 with p well 5. That is, when a voltage lower than that of terminal 16 is instantaneously applied to terminal 15, a current flows from terminal 16 to terminal 15, and minority carriers of electrons are injected into p well 2 from terminal 15. The electrons are also captured by the positive bias applied to terminal 12.
However, as the conventional double structured wells are structured as stated above, a parasitic bipolar transistor is formed with the n.sup.+ layer connected to terminal 13 being the emitter, p well 5 being the base, and n well 3 being the collector. Therefore, if terminal 13 is negatively biased strongly by a strong, external noise, a current flows from n well 3 to the n.sup.+ layer connected to terminal 13 by the bipolar operation. The arrows B in FIG. 1 indicate the direction of the current in a solid line and the direction of the flow of the electrons in a broken line. In this case, as there is a resistance component R.sub.z in n well 3, the portion 3a of the n well immediately below the n.sup.+ layer connected to terminal 12 disadvantageously assumes a negative potential rather than a positive potential, resulting in injection of the minority carriers into p well 2.
In another case, the conventional structure of the double structured wells has an arrangement of wells as shown in FIG. 2. A problem of a latch-up phenomenon in a conductor device of this structure will now be described with reference to FIG. 2.
At first, injection of electrons is caused in the n.sup.+ layer within a p well 25 surrounded by an n well 23 (see the arrow C of FIG. 2), the electrons enter a semiconductor substrate 21, and they pass a substrate resistor R.sub.s immediately below a p well 22 (the arrow D of FIG. 2). Accordingly, the base of a parasitic npn transistor 26 is biased, a base current flows, and a current flows into the n.sup.+ layer within p well 22 from an n well 24 by the amplifying effect of parasitic npn transistor 26. As a result, a current flows in a parasitic resistor R.sub.g within n well 24, the base of a pnp transistor 27 is biased, and a current flows into the p.sup.+ layer of n well 24 from p well 22 by the amplifying effect of pnp transistor 27. The bias of substrate resistor R.sub.s is thereby increased, applying a positive feedback to the operation above, resulting in a so-called latch-up phenomenon.
The injection of carriers above causes a store hold error in memory cells of a DRAM (Dynamic Random Access Memory), for example. Referring to FIG. 3, in this store hold error, the electrons are injected from the n.sup.+ layer of a p well 44 (see the arrow E of FIG. 3), the electrons penetrate into a semiconductor substrate 41, further enter a p well 42, and are captured by the n.sup.+ layer on the surface thereof (see the arrow F of FIG. 3). If the electrons captured by the n.sup.+ layer enter a storage node 45 of the memory cell, storage node 45 kept at a positive level attains a negative level, causing a store hold error. Injection of electrons into p well 44 is mainly caused in three cases shown in FIG. 4: a case where the pn junction of p well 44 and the n.sup.+ layer thereof is biased in the forward direction ([A] of FIG. 4); a case where a high V.sub.D is applied to the MOS transistor, a high drain current flows and hot carriers are generated ([B] of FIG. 4); and a case where irradiation of .alpha. rays is carried out, entering into p well 44, so that separation of a pair of electron and hole within p well 44 is caused ([C] of FIG. 4).